counter is automatically reset when 10
counts are registered (note that zero is
one of the counts). It is also important
to realize that many different types of
counters can be used here, but the concept is the same. (Refer to the previous
article on counter types in this column.)
The operation is straightforward.
The circuit counts normally for 10
counts. At the start of the 11th count,
the output of the AND gate immediately goes high and resets the counter to
0000. The AND gate output also goes
to zero when these bits change. In fact,
the output of the AND gate is an
extremely narrow pulse that is related
to the propagation speed of the circuit.
Often, this pulse is less than 10 nS and
can be difficult to observe. The pulse is
exaggerated in the figure for clarity.
There are several points concerning
the decoding of the outputs. An AND
gate will function properly without any
glitches as long as it is used to reset the
ripple-counter to zero. However, an
AND gate used to decode state nine of
a 16 state ripple-counter will show
glitches on some state changes beyond
nine. (The ripple delay is not as
significant a factor as it was for the
counters discussed the last time.)
With programmable logic devices,
the routing of the decode and reset
lines can cause problems. Not all of the
bits may be reset properly. In this case,
either use a synchronous counter design
or else use a separate reset flip-flop that
produces a predictable-length pulse.
These divide-by-N circuits can also be
cascaded to create any integer division.
Figure 4 shows a divide-by-1,005 circuit
(with a flip-flop reset). The operation isn’t
as complicated as it first appears. There
are three cascaded divide-by- 10 counters
that are basically the same as Figure 3.
FIGURE 3. Dividing by N is
a matter of choosing the
proper bits to AND together
to reset the counter. In this
case, the counter divides by
10. The reset pulse is greatly
exaggerated. It’s really only
a few nS long.
SERVO 01.2007 75