5 MHz Cycles
3.3333 MHz Cycles
Average of Cycles
signal and again, transmission line considerations will be required. This is not
too much of a concern with programmable logic chips where the internal path
lengths are very short. However, it is very
important with discrete designs.
Another problem with this approach
is the variation of the delay circuit. A
temperature shift can cause a significant
change in the output if an internal delay
is used. This is because the internal
speed of the gates and routing resources
changes considerably with temperature.
This is especially true with CMOS circuits.
It is possible that an XOR frequency
doubling circuit cannot be guaranteed to
work over a given temperature range.
Operation speed also depends upon the
power supply voltage. However, this is
usually a second order consideration
because most systems today regulate the
power quite well. But, if batteries are
used, this becomes an issue.
The external RC delay can generally
be made to be reasonably stable over
temperature. But because of stray
capacitance, the delay must be relatively
large. External stray capacitance usually
varies more from unit to unit rather than
with temperature and is often in the 10
pF range. Good layout can reduce this to
a few pF. Also, because the delay is now
off-chip, it is more susceptible to noise.
Of course, the tolerances of these components must be considered too.
Sometimes the instantaneous frequency is not as important as the
average frequency. If so, then there is
another approach that allows fractional
frequency division to arbitrary precision.
Suppose you need a 4. 5 MHz clock and
only have a 10 MHz clock. If you divide
10 MHz by two, you get 5 MHz. If you
divide it by three, you get 3.3333 MHz.
What you really need is to divide by
2.2222. But it’s not obvious how to do
that. The solution is to alternate between
dividing by two and dividing by three.
The value needed is closer to a
division by two than a division by three.
If the 10 MHz signal was divided by
two twice as often than being divided
by three, what would the result be?
There would be two 5 MHz cycles and
one 3.333 MHz cycle. The average
frequency of these four cycles is 4.444
MHz. This is an error of about 1.2%.
This is certainly much closer to the
desired value than is 5.0 MHz (error of
10%) or 3.3333 MHz (error of 35%).
This can be further refined as necessary
by adjusting the division ratios as need-
ed. In theory, this approach will allow
you to close in on your desired frequency to whatever accuracy you need.
This idea is based on the
mathematical principle that any rational number can be expressed by the
ratio of two integers. In this case, the
fraction is 2.2222. The easiest available
integers are two and three. It becomes
clear that it is possible to take a certain
number of twos and threes such that
their average becomes 2.2222.
The quick and dirty way to determine the proper ratio is by trial-and-error with the two division values that
bracket the desired value. Start with one
of each and determine the average. In
this case, 5 MHz and 3.3333 MHz average to 4.166 MHz. This is lower than
the target value of 4. 5 MHz so add
another 5 MHz cycle. Two 5 MHz cycles
and one 3.333 cycle average to 4.444
MHz. If this is not accurate enough,
continue adding a 5 MHz cycle if the
result is below 4. 5 MHz and add a
3.333 MHz cycle if the result is above
4. 5 MHz. The result will dither around
the value you want. Eventually, you will
reach a value that is as close as you
choose. As you can see from Table 1, an
exact solution occurs with seven cycles
of 5 MHz and 3 cycles of 3.3333 MHz.
Figure 7 provides a block diagram
circuit for the “perfect” solution. I chose
to alternate between the different
division circuits to
distribute the variations over the full
FIGURE 7. With
two simple counters, a frequency
will allow most
any output division ratio. In this
case, the input
10.0000 MHz and
the output frequency averages
4.5000 MHz for a
division ratio of
2.2222. The output consists of
seven 5 MHz
cycles and three
3.3333 MHz cycles.
78 SERVO 01.2007