(except for special cases). Most typically
the output is a relatively small pulse.
However, often something approaching
50% can be obtained for non-program-mable dividers by choosing the proper
counter bit as the “output.” For example, in the divide-by- 10 circuit (Figure 3),
bit 3 is on for 40% of the time.
One way to eliminate this is to follow
the divide-by-N circuit with a simple flip-flop to square the output (as noted
above). This works but has two drawbacks. The first is fairly obvious — the frequency is now reduced by 50%. Thus, the
primary division ratio must be changed to
compensate for this. The second problem
is a bit more subtle. The addition of the
squaring flip-flop limits the division values
to even numbers. It becomes impossible
to provide a final division ratio that is odd.
This makes more sense when examined from a mathematical perspective.
These divider circuits have the effect
of multiplying the period by an integer.
The final “squarer” flip-flop multiplies the
final result by two. Therefore, the final
result must be even because everything
multiplied by two is an even number.
It is possible to create symmetrical
waveforms with odd-division ratios but
it requires additional resources.
Basically, an extra flip-flop alternatively
adds and subtracts half of a clock to the
output. This evens out the asymmetrical
signal and creates a nice square wave.
The typical method for frequency
multiplication is with the use of a phase-locked loop (PLL). This is an analog
technique that is not usually available
for programmable logic. Digital designers tend to shy away from analog PLLs,
as well. This is regrettable because the
PLL has a lot of nice applications and
is not really that difficult to master.
Unfortunately, a proper discussion of
PLLs is too long to include here. There
are other analog frequency multiplication techniques besides PLLs, as well.
The typical method of frequency
multiplication for digital designers is to
use an XOR gate (exclusive OR). This
gate has a high output when the
inputs are different and has a low
output when the inputs are the same.
Figure 6 provides a simple circuit to
double an input signal. The operation is
fairly clear. The input signal is delayed
in some manner. This can be done by
using the internal propagation delay
through additional gates, internal
routing delays, or an external resistor-
FIGURE 5. A programmable divider uses
XNOR gates to match the bit outputs to
the desired values. When all the bits
match, the counter is reset. Note that
the “program” bits do not have to be
switches. Other flip-flops or logic circuits
could be used.
capacitor (RC) network. The result is a
pulse at the start and end of the input
signal. The pulse length is exactly equal
to the time interval of the delay circuit.
There are a number of issues with
this approach. The first is that the output
is usually a very narrow pulse of a few
ns. This means that high-speed concerns
will have to be examined. If a high-speed
input signal is used, say 40 MHz or so
(the most common situation), the output
will often be at a frequency where
transmission line factors will become
important. Short delay times (about 10
nS) create the equivalent of a 100 MHz
FIGURE 6. An input frequency can be
doubled with an XOR gate and a delay.
The output will be a pulse at the leading
and trailing edges of the input signal. The
pulse width will equal the delay.
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