with the data acquisition computer. The I2CHW module
was operated at a fast speed of 400K as an I2C master.
The UART speed was run at 38400 baud by driving the
UART module using the VC3 clock signal at SysClock/78,
where the SysClock was selected to be 24 MHz for both
the master and slave modules. The LCD module was used
to display information on the evaluation board screen.
The slave PSoCs had slightly different configurations,
with three PGA modules (one each for the x, y, and z axes),
one EzI2C module, and a TRIADC8 analog-to-digital converter. The EzI2C modules were operated at 400K as I2C
slaves, and their slave addresses were chosen to be unique.
The PGA gains were set to a fixed value of 1 (although
the code could be easily modified to set dynamic gains).
The TRIADC8 module was driven by the VC1 clock set to
SysClock/8, with references set to yield a range of 0 to 4
volts. All the PSoC modules were powered by 5.0V.
The software for this system utilizes a command-response architecture, where the commands (of exactly
one byte in size) always originate from the master, and
the responses (at least one byte in size) are always sent
by the slaves to the master. When the unit is powered on,
the master initializes its I2C and UART modules, and waits
for a few milliseconds for the slave to initialize its PGA,
ADC, and EzI2C modules. Upon completion of the
initialization phase, the slaves continuously poll the first
byte of their EzI2C receive buffer until one of the registered
commands is detected. Upon detection, a switch structure
is used to respond to a variety of pre-defined commands.
In order to signal the master that it is busy executing the
command, the slave places a NULL_CMD byte in its EzI2C
transmit buffer before start of command execution.
When all systems are ready, the master writes an
ADC_START command (all commands are #define-d) to
each of the slaves sequentially. The slaves respond to this
command by starting the data acquisition. While the master
Item# Manuf Dist.
PSoCEval1 Cypress Semiconductors
CY8C29466-24PXI Cypress Semiconductor
DE-ACCM3D Dimension Engineering
3M 2010/10 100SF
SR205E104MAR AVX Corporation
ECC-A3J120JGE Panasonic ECG
B37979N5101J000 EPCOS Inc
FIGURE 6: SAMPLE SIGNALS FROM A HIP-MOUNTED
ACCELEROMETER SHOWING THE VOLTAGE LEVELS FOR
VARIOUS EVERY-DAY ACTIVITIES.
waits for the completion of the data acquisition by the
slaves, it completes the UART transmission of data acquired
from the previous cycle. Such a strategy results in an
increased system throughput. Upon completion of the data
acquisition, the slave places the response data into its
transmit buffer, and precedes this data with a response
command (ADC_DONE, in this case). Meanwhile, upon
completion of the UART transmit operation, the master
PSoC evaluation board
PSoC mixed signal array
Buffered tri-axis accelerometer
Cable 28AWG, 10 conductors, 100ft
Capacitor 0.1uF 50V 20% radial
Capacitor 12pF ceramic disk, 6kV 5%
Capacitor 100pF 50V ceramic mono pm
Cystal 32.768kHz, 6pF 10
8-12 nos perf board 10
28 pin (2x14) solder tail dip socket 4
Connector header female 28pos, 5
0.1” pitch, tin
Connector DIP IDC 10Pos gold, gray 5
Connector header female 10pos, 5
1” pitch gold
Connector plug IDC 10pos .1x.1 pitch DIP 5
Bus extender 5
SERVO 12.2008 41