//delay for slave select
x = 0x83;
//illuminate both LEDs
The atomic clear operation we let loose on the TRISD
register set the direction of I/O pin RD9 to input. Writing a
zero (0x0000) to the SPI1CON register guarantees that the
ON bit is cleared which stops the SPI engine in its tracks.
The zeroing of the SPI1CON register doesn’t clear the data
buffer SPI1BUF. So, we must perform a read against
SP1BUF to clear it. With the SPI engine stopped, we can
configure it for our purposes.
The PmodJSTK datasheet sets a 1 MHz SPI SCK limit for
proper operation. To be safe, we’ll run our SPI SCK signal at
500 kHz. Here’s the math behind determining what to load
into the SPI1BRG register:
FSCK = FPB / 2 (SPI1BRG+1)
FSCK = 500 kHz
FPB = 8 MHz
Doing some quick head math tells us that we need to
divide the 8 MHz Peripheral Clock (FPB) by 16 to obtain the
500 kHz FSCK value. So, we load SP1BRG with a value of 7.
If you decide to run at the max SPI SCK rate, you’ll want to
divide FPB by 8, which means you’ll have to load 3 into
Clearing the SPIROV overflow bit infers that we will be
checking for overflow errors in our code. Let’s keep it
simple and not complicate our driver with error checking
until we’re sure we have some solid code under our belts.
However, it’s a good idea to go ahead and clear the
overflow bit as the SPIROV bit is not automatically serviced
by the PIC hardware and can only be cleared manually in
this manner. Note we used the SPI1STAT register’s atomic
bit clearing apparatus to clear the SPIROV bit.
All we have to do is set the Master Mode Enable bit in
SPI1CON for eight-bit Mode 0 operation. At this point, the
SPI1BUF is clear, the SCK clock rate is set, and all of the SPI
status bits are initialized. We’re ready to start the SPI
engine using the mspENBL macro as the key. Once the SPI
motor is running, we can release the brakes. The PmodJSTK
requires that its Slave Select line be driven low before any
communications sessions can be established. The brake
release in this case is the macro that drives the PmodJSTK’s
Slave Select line logically low, mjoystickON.
The PmodJSTK datasheet recommends that a delay of
at least 15 µS be observed following the activation of the
PmodJSTK’s SPI portal before beginning data transmission.
The little for loop I threw in as a 15 µS delay isn’t very
scientific but it works. We’re using the PmodJSTK’s LEDs as
activity indicators. So, I initially illuminate both LEDs by
clocking in the first byte with a value of 0x83 to give us an
immediate visual indicator of the PmodJSTK’s operation.
Now that our SPI machine is under way, let’s examine the
code that moves the data:
for(spIndex = 0; spIndex < 5; ++spIndex)
//red neck delay for slave
//wait until Transmit
SPI1BUF = x;
//send variable x
//wait for Receive Buffer
spDataIN[spIndex] = SPI1BUF;
//read the clocked in data
//deselect the slave
if(++x > 0x83)
//count 0x80 – 0x83 then
x = 0x80;
//extinguish the LEDs
//enable SS line
The PmodJSTK datasheet states that we should
SCREENSHOT 1. The bytes contained within the spDataIN
array are a result of my holding the joystick in an off-center
position while depressing the joystick handle to activate
the joystick switch.
50 SERVO 01.2010