SCHEMATIC 1. As you can see, the ZG2100M interface is simple. A master SPI portal, three command output pins, and a data interrupt
input at the PICtail Plus Interface controls the movement of data and the state of the ZG2100M.
conference. The Explorer 16 development board/ZG2100M
PICtail hardware we’ll be talking about here is smiling for
the camera in Photo 2.
The Explorer 16 posing in Photo 2 is equipped with a
PIC24FJ128GA010. A ZG2100M PICtail can also be seen
standing tall in the Explorer 16 development board’s
interface socket. Once we get this ZG2100M hardware
configuration loaded up with the ZeroG firmware driver, we
can migrate the design to a PIC platform of our own
The ZG2100M consists of a ZG2100 802.11b
transceiver, all associated RF components, a crystal
oscillator, the necessary glue components, and a printed
circuit board antenna. Just about any eight- or 16-bit
microcontroller with a native or emulated SPI portal can
utilize the ZG2100M’s radio facilities. With that, the UART
pins you see in Schematic 1 are intended for use as a
debug interface only.
When mounted on an Explorer 16, the ZG2100M is
powered by a 3. 3 volt supply. The ZG2100M can assume a
number of modes or power states. Thus, it is important to
understand how the ZG2100M’s CE_N pin’s logic state
affects its power consumption and internal operation.
Obviously, when both the VDD_ 3. 3 and CE_N pins are not
powered, the ZG2100M module is considered to be void of
any power. Applying 3. 3 volts to both the VDD_ 3. 3 and
CE_N pins forces the ZG2100M into hibernation mode.
When it’s hibernating, all of its internal circuits are turned
off which means that an external device must be used to
coerce the ZG2100M to enter and exit hibernation. Sleep
mode is entered when the ZG2100M is powered and the
CE_N pin is held logically low. The ZG2100M’s reference
clock and internal bias circuitry are enabled when it’s
PHOTO 2. The Explorer 16 development board is loaded with
a PIC24FJ128GA010 and ZG2100M PICtail. The Microchip
engineers have provided ZeroG code within the Microchip TCP/IP
stack to support this configuration.
SERVO 03.2010 43