CPLDs — Part 1
complex programmable logic devices
An Introduction
by David A. Ward
Anyone involved in the field of digital electronics should become familiar
with CPLDs or complex programmable logic devices. This article and those
that follow, will help you get started implementing CPLDs into your circuit
designs. CPLDs are ICs that can be programmed to replace many standard
74XX series ICs, as well as perform any logic functions that the 74XX series
can perform when combined together. The CPLD that will be explored in
these articles is the Xilinx XC9572XL in a 44-pin PLCC (plastic leadless chip
carrier) which can incorporate up to 1,600 logic gates in a single IC.
Although there are several manufacturers of CPLDs, these articles will only deal with the Xilinx brand. There are several reasons why Xilinx CPLDs are used. First, Xilinx provides their design, simulation, and programming software
(Xilinx ISE) for free. Second, you can purchase a Xilinx CPLD
programmer for $129; $89 for academic pricing. Third, you
can purchase the XC9572XL CPLD in a 44-pin PLCC package
which can readily be breadboarded using a standard 0.1”
breadboard and PLCC adapter board. Finally, Xilinx is one of
the largest — if not the largest — manufacturer of CPLDs in
the world, so learning how to use their products is a good
path to start down.
Before we delve into the XC9572XL CPLD, let’s take a
brief look at the history of PLDs or programmable logic
devices. In about 1978, PALs were introduced. These PALs
— or programmable array logic devices — were OTPs or one
time programmable devices. Once you programmed or
“burned” your logic into them, they could not be erased
and reprogrammed. Next came GALs — or generic array
logic devices — in about 1985. GALs are similar to PALs but
can be reprogrammed. CPLDs are essentially several GALs
inside of one IC, allowing for a much higher logic gate
count. PALs and GALs might be able to incorporate several
hundred logic gates whereas the Xilinx XC9572XL CPLD can
52 SERVO 03.2011
incorporate up to 1,600 of them. This CPLD also uses “fast
Flash technology” to retain the internal logic connections.
This means that this CPLD is non-volatile; it won’t lose its
information or configuration when power is removed from
the chip. It also means that it can be erased and
programmed up to 10,000 times. Xilinx datasheets rate the
XC9572XL CPLD data retention at 20 years.
Let’s take a look at Figure 1 to see what’s inside this
CPLD and see how it functions. The XC9572XL CPLD
contains 72 macrocells (that’s where the 72 in its part
number comes from); four function blocks times 18
macrocells per function block. A macrocell consists of an
“SOP” or sum of products structure. Each macrocell is
capable of up to 54 inputs and 18 outputs. The SOP
structure consists of arrays of AND gates with
programmable interconnections. This forms the “products”
part of the SOP structure as in Figure 2. Looking at the
AND gate truth table in Figure 3, you can see that it acts
or appears like multiplication. Several of the AND gates are
then connected to an OR gate for the “sum” portion of the
SOP structure. Looking at the OR gate truth table in Figure
4, you can see that it acts or appears like addition or
summing of the 1s and 0s.
Perhaps studying a simplified diagram of a CPLD —
without all of the details — will help clarify things a little.
