CPLDs — Part 3
complex programmable logic devices
by David A. Ward
After reading the first two articles in this series of five on CPLDs, you should be able to
enter a digital logic circuit into the Xilinx software through the graphical or schematic
entry method, compile that design, and program the configuration into a CPLD. This
article will demonstrate how to simulate your digital logic design in Xilinx Isim.
To begin with, enter the circuit you want to simulate into the Xilinx software. We’ll use a simple two-gate circuit with three inputs and one output (see Figure 1). We
won’t go into all of the details on how this was done; you
can refer back to the second article if you need to. We now
need to generate an HDL test bench that will describe the
signals we’d like input into our circuit for simulation purposes.
Select Project>New Source from the top menu as shown in
Figure 2. The next window asks which type of file we want
to add to the design; select VHDL Test Bench (see Figure 3).
It’s also a good idea to add the letters TB into the file name
so that whenever the file name appears, you can quickly
differentiate it from other types of files.
Figure 4 shows you which source file
the test bench file will be associated
with; in some designs, you may have
several source files open at one time. In
this demonstration, only one is open;
select Next. The next window that will
open is the summary window shown in
Figure 6; select Finish. Figure 6 shows
the HDL test bench template that was
prepared for you. Notice in Figure 7
that an area is marked between the
two green comment lines. That’s the
user defined section where we will
enter our test signal information into.
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