CPLDs — Part 4
HDL Programming
complex programmable logic devices
by David A. Ward
As we’ve mentioned in the previous articles in this series, HDL (or hardware
description language) is really the preferred method used to program CPLDs
versus the graphical or schematic method that has been demonstrated so far.
(We’ve used the schematic method up to this point because it’s an easier way
to get started programming CPLDs. Now that you have a better idea of what a
CPLD is and what it can do, it’s time to introduce and begin using HDL.
www.servomagazine.com/index.php?/magazine/article/june2011_Ward
Of course, in a single magazine article we’ll only be able to give a fairly brief introduction to HDL. There are many resources available online if you want to
learn more about HDL. I recommend The Low-Carb VHDL
Tutorial by Bryan Mealy. This is a good and concise resource
with many examples. HDL is also referred to as VHDL — the
“V” stands for a very high speed integrated circuit.
Although HDL may appear similar to some computer
programming languages, the end results are quite different.
When a computer language program is compiled, it is
compiled into machine instructions that the microprocessor
will execute one at a time in a sequential manner. When an
HDL program is compiled, it is compiled into
interconnections which will be configured into the CPLD.
When the CPLD is programmed with these
interconnections, the circuit will operate in a parallel or
concurrent manner. So, the order in which HDL lines are
entered into the HDL source code may not matter as far as
the final operation of the circuit is concerned. HDL is really
a description of a digital logic circuit rather than a set of
sequential operations to be performed, such as in a
computer program.
HDL programs contain two main sections: the “entity”
section and the “architecture” section. The entity section
comes before the architecture section and declares the
inputs and outputs of the digital logic circuit. The
architecture section describes how those inputs and outputs
from the entity section will behave in a digital logic manner.
Figure 1 is an example HDL listing for a two input AND
gate with inputs named A and B, and one output named X.
As you examine the HDL listing, note a few things. First,
HDL is not case sensitive, so that input “b” would be the
same as input “B.” HDL lines are terminated with a semi-colon (;). White space — extra spaces added for clarity — are
also ignored by the compiler. You can add comments where
you want after placing two dashes (—); this means that the
compiler does not attempt to compile anything after the
two dashes.
FIGURE 1.
FIGURE 2.
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