Getting
Started With
FPGAs —
Part 2
by David Ward
In the first article about FPGAs, the reader was introduced to the Digilent Basys2
FPGA trainer and the Xilinx XC3S100E 100K gate FPGA in a 132-pin surface-mount package. The reader was shown how to enter a simple two input AND
gate in VHDL, compile the listing, generate a configuration bit file, and
download that bit file into the FPGA and test it.
In this second and final article, we will demonstrate a more complex and useful digital design that will use the Basys2 FPGA trainer to control a scrolling message
on an 8 x 8 LED matrix display; see Photo 1. You will need
to use four of the Digilent expansion cables and all of the
16 available FPGA expansion pins to make this circuit
operate. The 8 x 8 LED matrix that is used is a Kingbright
PHOTO 1
62 SERVO 10.2011
part number TC15-11SRWA 1.5” dot matrix display from
www.kingbrightusa.com for $4.76. When you look up
the Kingbright matrix, you’ll notice that the top surface is
not red like in Photo 1. If you cover the surface with red
tail light repair tape, your letters appear brighter.
A complete schematic diagram is shown in Figure 1.
The cathodes of the LEDs in the matrix are connected to
the column pins which are then taken to ground through
eight 2N7000 FETs. Notice that no resistors are required
when using these FETs in the manner shown here. The
gates of the FETs are connected to the eight column
outputs from the Basys2 expansion connectors. Only one of
these FETs will ever be on at one time because a ring
counter will be used to sequentially scan through them one
at a time over and over again at a fast rate, giving the
illusion that all of the LED columns are lit at the same time.
In reality, a maximum of eight LEDs will ever be on at the
same time. Each FET will conduct (at the most) 80 mA at
one time; eight LEDs x 10 mA each = 80 mA. According to
the datasheets they are capable of conducting 200 mA.
The anodes of the LEDs are connected to the row pins
on the matrix. The rows will be driven by eight FPGA pins
from the Basys2 expansion connectors in series with eight
150 ohm resistors. These eight resistors are necessary to
limit the current from each FPGA row pin to 10 mA. The
LEDs drop 1.8V when conducting 10 mA. Therefore, 3.3V
(a LVTTL logic “1”) – 1.8V = 1.5V and 1.5V / 10 mA = 150
ohms of resistance. The FPGA pins can be configured in the
UCF file to drive 16 mA. There will not be any problems
driving the 64 LEDs in the matrix with the FPGA unless you
