attempt to energize more than one column at a time.
Now, let’s step through the VHDL and UCF listings line
by line and explain what is occurring; see Listings 1 and 2.
By the way, this code displays the message “A,” “B,” “C,”
and a blank as it scrolls from the right side of the matrix
over to the left. The code has been commented here and
there to help the reader see what is being done. Comments
in VHDL are made by typing in two dashes (“—“) and then
your comments. Comments are not compiled; they are
ignored by the Xilinx compiler. So, it won’t be necessary to
elaborate on the comment lines such as lines 1 through 3.
Lines 5 through 9 are the “Entity” section of the VHDL
code listing. This is where ports or actual input and output
signals are defined. Line 6 defines an input line named “clk”
which is a single bit. The UCF file will direct this to pin B8
of the FPGA where the Basys2 is connected to a 50 MHz
clock signal; see line 1 of the UCF file in Listing 2. Line 7
defines an eight-bit output port named DISPLAY_C<0>
through DISPLAY_C< 7>. These are the eight bits that will
go out to the columns of the LED matrix. Their locations are
defined in lines 3 through 10 of the UCF listing. Line 8
defines an eight-bit output port named DISPLAY_R<0>
through DISPLAY_R< 7>. These are the eight bits that will go
out to the rows of the LED matrix. Their locations are
defined on lines 12 through 19 of the UCF listing. Line 9
marks the end of the Entity section.
Lines 12 through line 56 are the “Architecture” section
of the VHDL code listing. This is where the logical behavior
of the circuit is defined. Lines 14 though 16 set up a signal
named ABC that is 256 bits wide. It is initialized with the
ones and zeros to display A, B, and C with a final blank screen.
Line 17 sets up a signal called low_clk. This signal will be a
lower frequency signal derived from the higher 50 MHz
signal coming into the clk pin. Line 18 sets up a signal called
SERVO 10.2011 63