to read the state of each switch:
You can see the Digital 1 brick’s bits represented in
hexadecimal in the left sector of the terminal emulator
The schematic depiction of the pushbutton tells it all. The
equivalent circuit is a simple SPST switch providing a logical
high to the pulled down Digital 1 I/O pin D0. Be careful and
don’t get lulled into a state of false security. The virtual
pushbutton transitions smoothly between logic levels. If
you’re going to port over to a real mechanical switch, you’ll
need to debounce the real switch in your final application.
The Push/Pull switch featured in Screenshot 9 takes the
pushbutton concept a step further. You can line up a
maximum of 32 push/pull switches to simulate logic levels
that could be presented to the PIC18F46J13’s I/O pins. The
push/pull switch configuration could also be used to supply
logic levels to logic gates and multiplexers.
An eight-bit Transparent Octal Latch (74LS573) can be
simulated by deploying banks of three-state switches. The
three-state switches can be positioned to present a logically
high, logically low, or high impedance state. When the three-state switch is at the Z position, other logic signals attached
to D2 are free to operate without any logical interference.
The final set of switches can be visualized as MOSFET
devices configured as open source and open drain. Let’s look
at the open source switch that is configured on I/O bit 3 in
Screenshot 11. When the open source switch is in the Z
position, the drive signal is removed from the P-channel
MOSFET’s gate. At this point, the PIC18F46J13’s I/O pin
being serviced by the Explorer’s D3 I/O pin is free of any
logical influence from the open source switch. Applying the
logic of the schematic snippet in Screenshot 11 tells us that
providing a drive signal to the MOSFET gate will result in
presenting 3. 3 volts to the PIC18F46J13 I/O pin. In the case
of the P-channel MOSFET, the drive signal is logically low.
However, the result at static I/O pin D3 is identical and a
logic high level is presented by the D3 pin. This P-channel
MOSFET switch concept is commonly used to form a logic
controlled solid-state power switch.
The operation of the last switch in the set should be
familiar to those of you that have used logic level MOSFETs to
drive higher voltage devices. The open drain switch is
identical to an N-channel MOSFET with its source grounded
and its drain open. Digital 1’s I/O pin D4 is set for high
impedance operation in Screenshot 12. Judging from the
hex readout, nothing is driving the N-channel MOSFET’s gate
and the D4 pin is left to float. Switching to the zero position
applies a logical high drive signal to the N-channel MOSFET
definitely turning it on. Turning the MOSFET on pulls D4 to
ground level. What do we have to do to get a logic high at
the MOSFET’s drain?
What would happen if we drove the floating MOSFET
drain with a positive voltage? We don’t want to apply 3. 3
VDC directly to the drain because that will release the
MOSFET’s magic smoke when it is turned on. So, we’ll insert
a resistor between the applied voltage and the MOSFET gate.
That’s easy enough to do. So, I’ve physically pulled up D4
The PIC18F46J13 is
counting in binary on
its PORT D and we're
capturing it all with the
SCREENSHOT 7. The addition of a 1.0
kHz clock source on bit 31 of the
In fact, the virtual LEDs match the logic
analyzer as far as logic levels are
SCREENSHOT 8. From left to
right the switches are open
drain, open source, three-state,
push/pull, and pushbutton.
Think of these switches as logic
sources instead of switches.
SCREENSHOT 9. Call upon
the push/pull switch
configuration when you need
a sticky logic level.
SERVO 01.2012 55