42 SERVO 08.2017
or RD_fast signal. A screenshot of the intended behavior
(taken from the hardware debug of the working design) is
shown in Figure 3. Notice that the “sda_in” and “scl_in”
signals captured in the debugger match the scope shot
shown later in Figure 7. The transaction is a general call
(I2C global address = 0x00) software reset (I2C command =
0x06), and there is no data read back.
Because I decided to write the interface design to
support seven-bit I2C addressing, the slave_addr [7:0] input
contains an “extra” bit at the least significant position
(slave_addr). This bit is in the position that would
normally indicate a read or write (R/W) for the I2C
Since every I2C transaction (whether read or write) uses
the R/W bit set to 0 for at least part of the transaction (see
I2C review below), I adopted the convention of always
presenting to the interface module a slave address shifted
left one bit, with a ‘0’ at the least
significant (rightmost) bit. The state
machine inside the interface design
is written to expect this, and will
change the least significant bit
when required by the RD or WR
The result is that a slave address
given as 0x60 in the device
datasheet (for example) must be
left-shifted to become 0xC0. Slave
addresses with a ‘1’ in the
slave_addr bit should never be
presented to the interface, or an
illegal I2C transaction may be attempted.
Review of the I2C Protocol
In between the acknowledge signal and the
complete/valid responses, I would need to write a state
machine to complete the required transactions. I used the
timing diagrams in Figures 4 and 5 as my working
description of I2C reads and writes. Figure 4 shows an I2C
read, which consists of two parts. Figure 5 shows a write
with a normal acknowledgement at the end.
SDA is the data signal and SCL is the clock signal. SDA
and SCL may be driven low by either the master device or
the slave device, or released (tri-stated) and pulled up to a
high level. This active low tri-state high topology allows the
slave or master device to drive SDA/SCL low during
acknowledgement, and prevents the master and slave
Figure 3. I2C interface timing diagram.
Figure 4. I2C read transaction with repeated start bit.
Figure 5. I2C write transaction with acknowledgement.