devices from contending with each other.
Only the master device is capable of
starting a read or write transaction.
The first part of any I2C transaction
begins with a START condition (SDA
driven low by the master while SCL
remains high), and then the seven bits
(A7-A1) of the slave device address are
clocked in by each rising edge of the SCL.
The eighth SDA bit (R/W bit) indicates
whether the transaction is a read or a
write. If the R/W bit is low, the I2C slave
device is being written. Otherwise, the
transaction is a read.
The ninth SDA bit (ACK) is an
acknowledgement from the slave device
to show that the device address is recognized and the slave
can accept the transaction.
There are two ways that the slave device can handle
the ACK bit. Most commonly, the slave device will hold the
SDA low and allow the tri-stated SCL to be pulled high,
clocking in a 0 at the master device to indicate that the
slave acknowledges the address and is ready.
However, some devices can implement a mode called
“clock stretch” or “clock hold” where the slave device will
drive the SCL line low until it is ready to accept the
transaction, and only then release the SCL line high (while
still holding the SDA low). While the Si1145 doesn’t
implement clock hold, the Si7020 sensor does4. Since I
intended to use the same I2C interface module with both
devices, I decided to implement the ability to recognize
In the case where the slave device does not use clock
hold but cannot accept the transaction, it will “not
acknowledge” (NAK) its address by letting the ACK bit go
high (clocked into the master by the rising edge of SCL).
This would be the case when the slave device was busy
(sensor measurement in progress, for example).
If that happened, the master device would read a 1 for
the bit, and be expected to STOP. The master could then
retry the transaction until a successful acknowledgement
was received. (A STOP condition occurs when the master
tri-states SCL and then SDA so that they are pulled high, as
shown in the bottom right side of Figure 6.)
Once a slave device has acknowledged its address, the
next eight bits can be one of three possibilities:
1. In the case of a read by the I2C master, the next
eight bits will be the register address (also called a register
sub-address/SA) of the particular slave register that will be
2. In the case of a write by the I2C master of a data
byte that does not require a register address, the next eight
bits are the data byte. (This type of write is often the case
for simple slave devices such as I2C muxes or when the
write is a global reset.)
3. In the case of a write by the I2C master to a specific
slave device register, the next eight bits will be the register
address that is going to be written.
The ninth bit in any of the above cases is another
acknowledgement bit, but this bit will not be clock
stretched. The slave device already acknowledged that it
was ready for the transaction by acknowledging the slave
In the case of a read, the transaction has the two parts
shown back in Figure 4. The first part is actually a write
transaction that writes the register sub-address to be used
in the second part of the transaction. Following a RESTART
condition, the slave address is presented a second time (this
time with a read bit) and the data bits are read back from
the slave device register that was written in the first part of
The eight data bits are driven low/pulled high onto the
SDA line by the slave device and external pullup. During this
time, the I2C master must allow the I2C target device to
either drive low or tri-state (pull high) the SDA line while
the master clocks in each bit. The acknowledgement bit
that follows the data byte on a read transaction is driven
low and clocked by the master I2C device to show that it
has received the data.
In the case of a write transaction, one or more data
bytes can be transmitted (many devices can accept more
than a single data byte), and then a STOP condition would
be sent. The STOP condition is indicated by SCL being high
while the SDA rises from low to high. The write transaction
occurs without the repeated start condition, and is
completed all at once as shown in Figure 5.
Both the Si1145 and the Si7020 have short sections of
their datasheets that explain the I2C interface, as well as
show the types of expected writes/reads that may occur.
It’s good to review these sections to see any peculiarities of
For example, the Si7020 will reply to a read of a
SERVO 08.2017 43
Figure 6. Si7020 two byte and three byte
read transaction with Checksum (CRC) 5.