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Figure 2. Top level PMOD
Since the clock would be coming in at 100 MHz and I
needed to operate the I2C interface at below 400 kHz, I
initialization followed by a series of commands. (The I2C
reset in this case refers to sending a broadcast reset
command on the I2C bus, rather than a reset of the logic in
the FPGA.) Figure 2 shows the concept.
The top level state machine also receives an interrupt
signal from the Si1145. This means the logic is able to
determine when a measurement is complete without
polling a register, or using a long wait interval. The receipt
of an interrupt — like the user pushbuttons — causes the
rom_addr signal to jump to another location in the ROM,
and read back a series of I2C commands to retrieve
measurement values from the Si1145.
Clocking and Pinout
The ARTY board used to test the design contains a
Xilinx XC7A35TCSG324-1L part with four headers suitable
for the PMOD sensor, and a variety of LEDs and pushbutton
I/Os.1 There is a single 100 MHz clock provided to the FPGA
which is much faster than necessary, but can be divided
down by a clock manager.
PMOD JA pin 2
set_property PACKAGE_PIN B11 [get_ports SCL]
set_property IOSTANDARD LVCMOS33 [get_ports SCL]
set_property PULLUP true [get_ports SCL]
These lines in the ARTY_PMOD_pinout.xdc file set the
location of the SCL signal in the design to pin B11 of the
package (which goes to the PMOD JA header pin 2), set
the voltage standard of the pin to LVCMOS33, and apply an
internal FPGA pullup on the signal. There are 10K ohm
external pull-ups on the PMOD board, but I wanted to put
an internal pull-up on the signal in case the design was ever
modified for use with an I2C slave that didn’t have the
external pull-ups present.
The locations of the general-purpose I/O for the ARTY
board are shown in Figure 3.
40 SERVO 09.2017