Normally, the “top” level interface that I
created would not really be the highest level
of logic using the sensor data. The
responses of the sensor would be written
into registers that an even higher level state
machine would use to make decisions. (For
example, that could be the state machine
for determining the next actions of a small
robot.) However, I wasn’t ready to fully
integrate the sensors with my robot, and
just wanted to test the interface and sensors
to make sure they were working.
Implementation in Vivado
Simulation would be possible if I had an
HDL model for the PMOD, but I did not. So,
I planned to test the design in hardware. To
do that, I needed to make sure that the
data coming back from the PMOD sensor to
the top level state machine was not
optimized out. For those who haven’t
worked with FPGA synthesis and
implementation tools, consider that the
tool’s job is to make the design as small as
possible while preserving functionality. Anything that
doesn’t contribute in some way to the output at the pins of
the FPGA will be removed.
The best way that I have found to prevent Vivado from
optimizing away portions of the design is to bring
information (the data bits returning from the sensors) to
the pins of the device. Provided the tool cannot see a flaw
in the code that results in the output bits being a static
value, there is no way it can remove any logic that
contributes to the result.
If sufficient I/O pins aren’t available, take the
interesting data bits and XOR them together to get a single
bit result. Then, bring that to an I/O pin.
The project as set up in Vivado looks like Figure 4. The
entire set of Verilog source files (top.v, clock_module.v,
i2c_interface.v, and i2c_setup_rom.v) are shown in the
SERVO 09.2017 41
Figure 3. ARTY board general-purpose I/O pin locations.
Introducing the ME Labs D-Stick!
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