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this should look. (Ignore
the small board on top of
the RJ- 45 connector.)
The Vivado project (as
set up in Part 2) should
look like Figure 3. The
entire set of Verilog
source files (top.v,
shown together with the
_pinout.xdc) in the
Sources tab at the top
center. Below that in the
Statistics view, are the
counts of device resources
used by the
The left-hand Flow Navigator pane shows the processes
available for the source files, and the right-hand window
shows a piece of the Verilog code for the i2c_interface.v
Creating the project is straightforward, and requires
creation of a new project in Vivado targeting the XC7A35T-
1LI part; adding the five files (Verilog plus constraints); and
then running the synthesis, implementation, and generate
bitstream steps from the Flow Navigator pane (right click >
run). The design should run through the generate step with
warnings (but not critical warnings or errors) that can be
In the Flow Navigator pane, expand the Open
Hardware Manager selection, and click on Open Target.
Select Open New Target, and then Next. Leave the selection
defaulted to Local server, and click Next again.
Provided the board is powered, the cable is connected,
and the Vivado cable drivers have installed properly, the
board should be recognized. If not, double-check those
The next selection determines the JTAG clock frequency
used to connect with the debugging design inside the
FPGA. One of the most frustrating
experiences I’ve had with the Vivado tool is
when working with very slow logic (I2C, SPI,
etc.). The JTAG clock frequency should be
substantially slower than the slowest clock in
the FPGA that is going to be debugged.
In this case, I found that with the 4.6875
MHz clock, selecting a 2 MHz debug clock
caused intermittent problems with the
hardware debug windows, but the 1 MHz
debug clock was reliable.
Faster JTAG clocks should be avoided. Set Figure 5. Selecting download bitstream and probes files.
Figure 4. Setting JTAG clock frequency for debug.
Figure 3. Vivado design project (ARTY board SiLabs PMOD interface).
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