with a second global clock buffer (BUFG) is not a
“good” FPGA design practice because clock timing
cannot be traced through the counter logic. But for
the very slow resulting clock (200 kHz range), the
approach was acceptable as long as the slow clock
was distributed on a global clock buffer (BUFG). The
resulting power savings of 84 m W was necessary for
a battery powered robot.
As a second possible way of saving power, I
investigated what could be done with the divider and the
CORDIC. The divider uses 1,285 flip-flops, 598 LUTs, and
consumes 9 m W. The CORDIC takes an additional 1,067
flip-flops, 1,060 LUTs, and consumes 10 m W. (For power by
hierarchy, see Figure 14.)
These two blocks together are larger than the
remaining logic (1,198 flip-flops and 1,160 LUTs). Although
I could see no way to eliminate the divider functionality, I
did find a way to timeshare the divider core between the
calibration and calculation logic.
Since the CORDIC only computes the arctangent with
X/Y inputs bounded in the range of 0 to 1 (angles from 0
to /4 on the unit circle), I could replace the block with a
single 18 Kbit block RAM configured as a look-up table. The
power of a single BRAM was less than 1 m W in the
estimator, so the savings would be almost 10 m W, and the
change would simplify the design. This replacement will be
something that I implement in the next design iteration.
Conclusion & Next Steps
In building a new robot with a rotating microwave
sensor, I wrote Verilog FPGA code and used an HMC5883L
(GY-271 module) to implement a magnetic
compass/navigation system. The compass supplies vehicle
heading information for a motor controller, and will later
send azimuth information to a sensor.
Doing this development in an FPGA, I leveraged a
previous I2C interface design, and wrote code or used IP
cores for compass calibration and arctangent computation.
Taking some effort to reduce power, I kept the total design
to 85 m W, and have ideas of how to further reduce power.
The compass controller code is useful for a variety of
other small projects, or could be used “stand-alone” with an
appropriate interface. SV
Figure 14. Vivado design power estimate by hierarchy (~ 10
m W for CORDIC).
Figure 13. Vivado design final power estimate (~85 m W for
MICRO LINEAR ACTUATORS
Make your machine move
SERVO 12.2017 45