10 cycles. It is certainly possible to use seven consecutive 5 MHZ
cycles followed by three consecutive 3.3333 MHz cycles. The
design might be marginally easier.
Whichever approach is selected, an additional counter
and number of additional gates is needed. With this
example, a total of 10 flip-flops is required. This uses five of
the Xilinx 3000-series CLBs (Configurable Logic Blocks). But it
saves an extra crystal and two capacitors which reduces cost
and size and improves the reliability. Additionally, the output
is perfectly synchronized with the input clock. There is no
concern about frequency drift between the clocks.
You don’t have to use divisions by two and three. Any
two values can be incorporated as long as one is greater than
and one is less than the target. You can use three values or
more. However, using the closest integer values creates
the least amount of variability in the output signal. And,
realistically, this approach works best if the ratios are small.
(A ratio of 1,077 to 1,993 may make the output signal
perfect, but it’s going to be impractical to implement.)
There are a number of ways to change the frequency of
a signal. Some are simple and direct, while others are more
complicated and subtle. The approaches presented here are
not exhaustive but represent the majority of typical applications. Being able to control the frequency and timing of your
design is useful and important. SV
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