SCHEMATIC 1: Note that the VM voltage —
which is the product of a simple voltage
divider — has been rerouted to the analog-to-digital input at RA0. Otherwise, the BLDC
motor controller circuit is following the
hardware design we laid out last month.
PWM4
PWM5
PWM3
PWM2
PWM1
PWM0
R26
1K
LED9
R25
1K
LED8
R24
1K
LED7
R23
1K
LED6
C2
.1uF
R22
1K
LED5
C1
.1uF
R21
1K
LED4
R3
10K
C4
0.1uF
C3
0.1uF
5V
5V
R1
100
R2 1K
ICSP CONNECTOR
3
3
2
1
2
1
6
5
4
6
5
4
1
RB0/PWM0
21
RB1/PWM1
22
RB2/PWM2
23
RB4/PWM5
25
24
RB5/PWM4
26
27
MCLR
28
RB6/PGC
RB7/PGD
RB3/PWM3
AVDD
7
R6
470
VDD
20
C7
0.1uF
2
RA0
3
RA1
4
RA2
5
RA3
6
RA4
U1
OSC1
9
OSC2
10
19
AVSS
8
GND
PIC18F2431
RC2/CCP1
14
12
RC1/FLTA
13
RC7/RX
RC6/TX
18
RC5
17
RC4
16
RC3
15
11
RC0
VM
12V
R13
1K
LED3
R14
11K
R15
1K
Y1
5MHz
C6 20pF
C5 20pF
FAULT_I
LED11
PHASE_A
PHASE_B
PHASE_C
R12
1K
LED2
R4
1K
R11
1K
LED1
R5
1K
LED10
MOTOR_I
10K
R19
R20
100
5V
R7
10K
R8 200
R9
10K
3
2
1
POWER
12V
J1
3
SPD_REF
2
POT
1
5V
JUMPER BLOCK
R10 200
5V
5V
SW1
SW2
46 SERVO 02.2009
