input of the internal LDO (Low Drop-Out) voltage regulator.
Unlike the VBB input, the MCP2021’s internal voltage regulator
doesn’t need any help from its friends. The MCP2021’s voltage
regulator is thermally protected and shuts itself down in
short-circuit and overload situations. Depending on the type
of MCP2021 you specify, the internal voltage regulator’s
output can supply + 3.3V or + 5.0V at 50 mA over the
MCP2021’s entire operating temperature range (- 40°C to
+125°C). Our LIN node design uses the five volt version of
the MCP2021 (MCP2021-500). A 10 µF aluminum electrolytic
acts as the LDO voltage regulator input filter capacitor.
If overall footprint is important in your LIN node design,
the 10 µF aluminum capacitor can be replaced with a smaller
1.0 µF monolithic ceramic part. Just make sure that the input
filter capacitor you select can withstand the voltages applied
at the VBAT pin. Extra noise filtering at the voltage regulator
input is provided by C4, a 0.01 µF ceramic capacitor. Auxiliary
power input J1 has been added to the LIN node design for
your convenience. Power receptacle J1 parallels the VBAT input
to allow the easy connection of an alternate power source.
For instance, you can use J1 to power the node or cluster
from a wall wart if there is no VBAT voltage source available.
J2’s bidirectional LIN pin is an open collector driver that
is controlled by the voltage level applied to the MCP2021’s
TXD pin. In receive mode, the signal level presented to the
LIN pin is reflected logically at the RXD pin. TVS diode D4
is an SAE-recommended part that is used in LIN nodes to
protect the node from EMI and ESD transient surge voltages. D4 breaks down at 27.0 volts. I didn’t see anything
in the datasheets and application notes that labeled the
MMBZ27VCLT1 as an optional component. So, I suggest
keeping D4 in the face of the MCP2021 at all times.
Jumper JP1 is the master node jumper. When JP1 is
installed, switching diode D3 and resistor R4 form what is
termed the master node termination which provides a
strong pullup to the LIN bus recessive state (logical 1).
When the master node jumper is absent, the MCP2021
internally terminates to the LIN pin with a 30K resistor. Only
one LIN node in a cluster can be deemed the master node.
When all of the nodes in a cluster are sleeping, the cluster’s
master and slave node receivers are all listening to the
LIN bus. When there is no bus activity, the D3/R4 pullup
38 SERVO 06.2009
combination holds the LIN bus in a recessive state.
The right-hand side of the LIN transceiver interfaces to
the node’s host controller, which in this case happens to
be a PIC18F2620. The MCP2021’s LDO voltage regulator
output is presented at its VDD pin. Both variants of the
MCP2021 require an external output bypass capacitor for
stability. Ceramic capacitors C5 and C6 serve this purpose.
The open-drain /FAULT/TXE pin doubles as the Fault
Detect output and Transmitter Enable input. Faults include
a shorted-to-ground LIN bus and thermal shutdown.
Otherwise, driving the /FAULT/TXE pin logically high with
the PIC18F2620 enables the MCP2021’s LIN transmitter.
The CS/LWAKE pin may have a dual purpose, but it is
not a bidirectional pin. The CS portion of the pin’s function
is Chip Select. CS must be logically high to activate the LIN
transmitter. If CS is logically low when power is applied to
VBB, the MCP2021 enters Ready mode, which is also
defined as low power mode. In Ready mode, the MCP2021’s
receiver and voltage regulator are active while the transmitter
is inactive. Conversely, if CS is logically high at VBB powerup,
the MCP2021 enters Operation mode following the
stabilization of the voltage regulator output. The transmitter,
receiver, and voltage regulator are running in Operation
mode. LWAKE is short for local wake-up. The CS/LWAKE pin
is internally pulled down allowing an external switch and
pullup resistor to trigger a wake-up manually.
The MCP2021’s TXD pin is internally pulled logically
high to the output of the internal voltage regulator. When
the transmitter is enabled, the LIN pin logically follows the
voltage level of the TXD pin. If the voltage regulator output
voltage falls below 1.8 volts, the TXD pin is internally forced
high. There’s nothing fancy about the RXD pin. It is simply a
CMOS output that follows the logic of the LIN pin when
the receiver is operational.
As a master node, the PIC18F2620 will run both a
master node and slave node task under the strict control
of the 20 MHz clock. The only difference in a slave node
configuration is the absence of a jumper at JP1 and the
20 MHz crystal. A slave node needs no crystal-controlled
clock because the beginning of each LIN frame includes an
autobaud chirp (binary 01010101) that the slave nodes pick
up and use to set their baud clocks. The maximum baud
rate for a LIN cluster is 20 Kbps. The closest we can come
to that with the PIC’s EUSART is 19200 bps.
The ICSP programming/debugging portal is the same
circuit you see in most all of my PIC18 designs. However, be
careful what you use to program and debug this particular
LIN node hardware. Recall that the MCP2021 voltage
regulator is rated to safely supply 50 mA of current. As you
can see in Figure 1, that eliminates the MPLAB ICD2 as a
node-powered programmer/debugger. I had no problems
programming the LIN node’s PIC18F2620 with an MPLAB
ICD3 and MPLAB REAL ICE using power provided by the
PHOTO 2. The LIN protocol has many advantages. However,
you can also use this board to transmit and receive standard
RS-232 messages on a single-wire, half-duplex link.
