We won’t worry about the RS-232 baud rate as we
don’t know what speed has been defined at this point. The
same goes for the ICD and analog-to-digital converter
declarations.
The PIC16F882’s general-purpose registers begin at
address 0x20 in Bank 0 and so do the eM8’s variable
registers which are the same thing as SRAM. Here’s how
each eight-bit memory location is allocated in assembler:
; Bank 0 address
CBLOCK 0x20 ;Define GPR variable register
locations
PAB
PBB
PCB
CNTL
CNTH
CNTDL
CNTDH
gb4
; gb5 ; general buffers
; gb6
; gb7
ENDC
;Port A Buffer
;Port B Buffer
;Port C Buffer
; timer low
; timer high
; counter devider low
; counter devider high
In the case of C, the CCS compiler does all of the
hard work. All we have to do is ask for some SRAM space
like this:
int8 PAB;
int8 PBB;
int8 PCB;
int8 CNTL;
int8 CNTH;
int8 CNTDL;
int8 CNTDH;
int8 gb4;
//Port A Buffer
//Port B Buffer
//Port C Buffer
//timer low
//timer high
//counter divider low
//counter divider high
//general buffers
The 96 bytes of general-purpose registers that begin at
address 0x20 in Bank 0 end at address 0x7F in Bank 0.
There are 32 bytes of SRAM area in Bank 1 between
address extents 0xA0 and 0xBF. The PIC16F882 datasheet
states that it contains 128 bytes of SRAM; now you know
where every byte resides.
A couple of assembler constants are declared next:
;******** Constants ********************
CNTDLR equ 0x64
CNTDHR equ 0x01
If you’ve had the chance to read my recent CCS C
compiler handbook Master And Command C for the PIC
MCU, the following C statements will come as no surprise
Sources
Queensland University of Technology
eM8
(Please contact Sam Wallace at: eM8@qut.edu.au
for contact information and product details.)
CCS
CCS C compiler
www.ccsinfo.com
54 SERVO 11.2010
to you. Here’s the C interpretation of the assembler
constants:
#define CNTDLR
#define CNTDHR
0x64
0x01
As you have seen, the programmer must keep up with
SRAM usage when writing the code using assembler. Let’s
work through this set of assembler SRAM allocations:
;******** Access REG **********************
; Access registers are used by several calls
; and services
DBL equ
DBH equ
APL equ
0x71
0x72
0x73
APH
equ 0x74
UF equ
CF equ
DS_READ equ
gb0 equ
gb1 equ
gb2 equ
gb3 equ
DPOINT equ
FSR_Store equ
w_temp equ
; Data pointer Low
; Data Pointer High
; Address Pointer
; Low
; Address pointer
; High
0x75 ; User Flags
0x76 ; Control Flages
0x77 ; input from dip switches
0x78 ; temp buffers
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
status_temp equ 0x7F
; variable used for
; interrupt context
; saving
; variable used for
; interrupt context
; saving
I’ve intentionally eliminated the user flags and control
flags since we’ll create C structures to hold the flag bits. I
also didn’t include the w_temp and status_temp allocations
as C takes care of saving and restoring the interrupt context
information. I’ve chosen (for now) to keep the FSR_Store
although I have a gut feeling we’ll be nixing that entry, as
well. Here’s the initial pass at the C port:
//Access REG
int8 DBL; //Data pointer Low
int8 DBH; //Data pointer High
int8 APL; //Address pointer Low
int8 APH; //Address pointer High
int8 DS_READ; //input from DIP switches
int8 gb0,gb1,gb2,gb3; //temp buffers
int8 DPOINT;
int8 FSR_Store;
The bits within the UF and CF SRAM locations are the
next elements to be defined in the assembler source:
;***** User Flags BIT Def UF
NU equ 0x0
DBu equ 0x1
TK equ 0x2
SW_CH equ 0x3
BCD0 equ 0x4
BCD1 equ 0x5
TPWM equ 0x6
; debounce control buffer
; tick set from timer 0
;change in reed switch
;BCD Display Counter
;BCD Display Counter H
;Display and read dip
;switch off
ADCR equ 0x7 ;AD New Read
;****** Control Flages CF
FQ
TRG
equ
equ
0x3
0x4
CNT_ON equ 0x5
;used for FQ mode select
;trigger bit used to store
;last trigger
;counter on bit counter
