Servo - June 2011

FIGURE 6.

Completed box.

down on the board after having the connector slots cut out. This allowed a cleaner look at the connectors and simple labeling.

The completed hardware is shown in Figure 6 and Figure 7.

Software

The next challenge was to update the firmware with a FIFO to allow for improved performance over the simple operation in the original design. The idea is that by adding some form of buffering, a larger number of bytes in a transmission can be monitored. The bottleneck here is the speed of the UART in getting the detected SPI bytes out to the terminal. The PIC is limited to using 57600 baud maximum, so if we buffer up the bits we can collect them from the SPI bus while we are pumping them out to the PC. A FIFO

FIGURE 7. Completed project.

FIGURE 8. FIFO fill code.

SPI Mode Configuration

The modes for the SPI bus can be a bit confusing partly because of the terminology, but it is really quite straightforward. There are four basic operating modes logically named: 0, 1, 2, and 3. These simply refer to the combinations of whether the clock signal idles low or idles high, and whether the data is latched into the receiving device on the rising edge or falling edge of the clock. (Please refer to Figure A for discussion.)

When data is sent out of the SPI port, the clock starts out in an idle state. This state is set by the CPOL signal. This can be seen in Figure A, where the CPOL signal is 0. The clock starts out low and ends low, and when the CPOL is 1, the clock starts out high and ends high.

When data is sent out of the SPI port, the clock edge selected by CPHA latches the data in the middle of the active data time using either the rising edge (CPHA = 0) or falling edge (CPHA = 1). In addition, this defines when the data line transitions to the next bit (the X part of the waveform in Figure A) which occurs on the opposite edge of where the data is latched on.