FIGURE 8.
FIGURE 9.
FIGURE 10.
you (Figure 10).
Notice in the HDL template that the
entity section is already completed for you, if
you entered port names and directions from
the earlier Define Module window; refer
back to Figure 8. Notice also there are
several lines of comments following two
dashes which are green in color. The only
real code or instructions that the compiler
will use — other than the entity and
architecture sections — are the library and
use instructions on lines 20 and 21. The
architecture section, however, is not
completed for you.
Figure 11 shows the HDL code for the
AND gate entered into the architecture
section. From here on, everything is
accomplished the same as it was when
entering a schematic circuit. Select
Implement Top Module (the green play icon)
and if it compiles okay, you can go on into
the Impact program and program your
CPLD. If there are errors in your source code,
error messages will be displayed in the
console window at the bottom of the
Navigator screen showing you which lines
had problems. We won’t go into all of the
details how this is done here; you can refer
back to Part 2 to see all of the steps to go
through to compile and program a CPLD.
FIGURE 11.
FIGURE 12.
SERVO 06.2011 51
