FIGURE 13.
FIGURE 14.
FIGURE 15.
FIGURE 17.
52 SERVO 06.2011
FIGURE 16.
All of the other basic logic gate
functions can be entered in the same way
the AND gate was; refer to Figure 12.
One of the most common methods
used to plan and design digital logic circuits
is to use a truth table. Let’s look at one way
to enter truth table information into HDL
code, (Figure 13). Let’s look at what is
taking place in this HDL listing. Line #32
begins the entity section. Line #33 defines
three inputs named A, B, and C, that are
defined as STD_LOGIC types of inputs. Line
#33 also illustrates how comments can be
added after the HDL code using the two
dashes.
The inputs could also have been
declared as BIT types “:IN BIT.” A BIT type
can either be a ‘1’ or a ‘0’, and nothing else.
A STD_LOGIC type can be a ‘1’ or a ‘0’ or
several other things, as well. A STD_LOGIC
can also be a ’Z’ (high impedance; a ’-‘
(don’t care); an ‘X’ (unknown); an ‘L’ (weak
‘0’), or an ‘H’ (weak ‘1’). When the Xilinx
program sets up your HDL template, it
usually defines the pins as STD_LOGIC. Line
#34 declares an output named “X” as an
STD_LOGIC type.
Line #35 ends the entity section. Line
#36 is white space which is ignored by the
compiler. Line #37 begins the architecture
section. Line #38 defines a locally used
SIGNAL named BITS_IN which will only be
used in the architecture section. It sets up a
three-bit STD_LOGIC_VECTOR which will be
used to hold A, B, and C so they can be
evaluated together rather than one at a
time. Line #39 is the begin label which is
necessary inside the architecture section.
Line #40 concatenates the three inputs
A, B, and C, and puts them into BITS_IN so
they can be evaluated together. Line #41 is
white space. Line #42 sets up the WITH
SELECT WHEN structure. Line #43 will make
the output or X a 0 when the three inputs
