Servo - June 2011

buffer is a perfect choice for this feature. The SPI data fills the FIFO by a simple read into the FIFO when the bytes appear at the SPI input port. The FIFO is drained by the program as it sends the data out to the PC via the PIC’s UART using printf statements. I chose to put the SPI FIFO filling portion in an interrupt handler which is very easy to use in the CCS environment. The FIFO drain capability resides right in the main loop of code (in fact, it does little else). The code sections are shown in Figure 8 and Figure 9.

The FIFO is implemented as a buffer of 60 bytes called DataBuffer. The incoming SPI byte is inserted into the DataBuffer (an array) at the current location pointed to by the InPos index. After this, the index pointer is checked to see if it is at the end of the FIFO and if so, the index is wrapped back to the top position in the FIFO (set to 0).

The drain operation works similarly, except the data is removed from the currently pointed to location via OutPos. OutPos is then checked to see if it is at the end and if so, it is reset to the top. This is elaborated on in Figure 10. That pretty much covers the FIFO part.

The next item to handle was the configuration of the SPI bus. It seems to me that there is always one element of a project that appears to be straightforward and then turns into a snake pit. That was the case here. I wanted to implement the SPI configuration as fully as I could, so the goal was to cover all of the four Because I had implemented the SPI receiver on the hardware SPI port, the setup of CPOL and CPHA signalling was just a matter of setting the appropriate bits in the registers for that port. Microchip has kind of a funny way of labeling these signals in the registers which required significant noodling to get right (and Googling). On the transmitter side, I had implemented the port using the built-in functions for a soft SPI interface. I was not able to figure out how to change the settings of the port at run time since the port configuration is done through a compiler directive. So, in order to complete my mission, I had to write a bit-banged SPI transmitter which appears in

FIGURE 9. FIFO drain code.

the listing in Figure 11.

After considerable head scratching, I managed to get the bits on and off at the right times and voila ... data was flowing. I tested the process by pumping out the data from the SPI port and looping it back to the receive side. I also monitored the data lines with a scope.