Servo - September 2011

Introducing the

Cypress PSoC 5

by Lloyd Moore

www.servomagazine.com/index.php?/magazine/ article/september2011_Moore

Cypress Semiconductor recently introduced the PSoC 5 processor and a line of development kits using it. For those not familiar with the Cypress PSoC line, the term PSoC stands for Programmable System on Chip, and it is what makes this particular line of processors unique. For many applications, additional hardware is not needed or is greatly reduced.

Not Just Another Processor

Figure 1 shows a simplified block diagram of the PSoC 5 processor. The PSoC 5 has the normal collection of on-chip resources you expect in a modern microcontroller such as: a processor core, Flash memory, RAM, counters, timers, analog-to-digital converters (ADC), and on-chip oscillators. In addition to the standard peripherals, there are blocks of software-configurable digital and analog resources. These are what make the PSoC processors unique.

The Digital Subsystem

The digital subsystem is where the PSoC family really shines. There is a small collection of dedicated hardware on the chip. Dedicated communications peripherals include: CAN 2.0, I2C, and a full speed ( 12 Mbps) USB 2.0 transceiver. Four dedicated eight-bit timer blocks implement timers, counters, and PWM functionality. Each of the timer blocks is configurable for the specific function being performed. Two timer blocks can also be combined for 16- bit functionality.

The digital subsystem includes up to 24 Universal Digital Blocks (UDBs). UDBs are unique to the PSoC family and are used to implement all the rest of the digital peripherals typically found in a microcontroller. The easiest

PSoC 5 - CY8C5588

Processor and Memory Core EEPROM Flash Cortex M3 CPU Program / Debug / Trace SRAM External Memory Interface DMA System Wide Resources Xtal Osc Internal Osc Low Freq Time Dog Reset & Power Monitor Charge Pump Digital Subsystem CAN 2.0 I2C Master / Slave Full Speed USB 2.0

Osc Real

Clock Watch

Dedicated Timer Block Timer Block UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB Dedicated Timer Block Timer Block CapSense LCD Direct Drive Analog Subsystem SC/CT Block SC/CT Block SC/CT Block SC/CT Block Amp Op-Amp Cmp Cmp DAC DAC DAC SAR ADC Del-Sig ADC Op-Amp Cmp SAR DAC Digital Filter Block Temperature Sensor Op-Amp Cmp

Dedicated

Op-

ADC Aux ADC

FIGURE 1.

way to think about UDB blocks is to think of them as an arithmetic logic unit (ALU) of a conventional processor with a bank of programmable logic attached. Figure 2 shows a block diagram of a UDB. At the top of the diagram is a block containing control logic for clock and status functions. Beside this are two blocks of programmable logic — essentially a PLD. Each of these blocks has the capacity to handle an eight product term Boolean expression. The programmable logic blocks can also be combined for more complex expressions.

The Datapath block contains a set of working registers along with a three-stage ALU. Everything in the Datapath is eight bits wide. First, the ALU stage performs one of the following operations: pass-through (NOP), increment, decrement, addition, subtraction, XOR, AND, or OR. Next, the shift stage performs one of four operations on the ALU result: pass-through, shift left, shift right, or nibble swap. Finally, the shifter result is masked and the final result is

44 SERVO 09.2011

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