FIGURE 1.
FIGURE 2.
FIGURE 3.
demonstrated later on (see Photo 2). The Basys2 FPGA
board comes equipped with eight slide switches, four
pushbuttons, eight LEDs, four seven-segment displays, a
VGA connector, a PS2 connector, and a USB connector. It is
powered by your PC’s USB connection or from an external
3.5V to 5.5V DC source.
FPGAs are volatile devices. That is, their configuration
bit file — the file that tells them how to make their internal
connections to perform the functions that you desire — is
lost each time the FPGA is powered down. Therefore,
FPGAs must have an external non-volatile memory device to
hold this configuration bit file. The Basys2 FPGA board has
a 2M bit Xilinx XCF02 non-volatile platform Flash PROM
(programmable read only memory) chip on-board for this
purpose. However, it is possible to download a
configuration bit file from your PC directly into the FPGA
and have it run as long as power is connected to the board.
If you want your configuration bit file to operate after
powering the board down, you will need to load that file
into the PROM instead.
Let’s look at the internal structure of the Xilinx
XC3S100E FPGA. At the most fundamental level in the
FPGA is the LUT (look-up table). Each LUT in the FPGA has
four inputs and one output, and any four variable Boolean
logic operations can be implemented into one LUT. If more
inputs are needed, the LUTs are cascaded together. There
are “G” LUTs and “F” LUTs; see Figure 1.
Two LUTs, one G LUT, and one F LUT are combined
together to make what is called a SLICEL, as
shown in Figure 2. When two LUTs are
combined together with a 16-bit RAM
register, it is called a SLICEM; see Figure 3.
There are a total of 1,920 LUTs in the FPGA:
960 G LUTs and 960 F LUTs. Since SLICEMs
have a 16-bit RAM register, they make up a
total of 15,360 RAM bits; 960 x 16 =
15,360. This is what is referred to as
distributed RAM in the FPGA. These 16-bit
SLICEM registers can also be used as shift
registers.
Four slices, two SLICELs, and two
SLICEMs are interconnected to make a CLB
(configurable logic block). There are 240
CLBs in this FPGA. CLBs are placed in rows
and columns; 22 rows by 16 columns for a
total of 240 as shown in Figure 4. Notice
FIGURE 4.
56 SERVO 09.2011
